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Advances in signal processing hardware are enabling the use of smart antennas and digital beamforming in communication systems for better reception and more users in the same amount of spectrum. Multi-channel digital beamforming is so computationally expensive that only reconfigurable hardware is capable of implementing it in real time.
Such systems require the coordination of large numbers of DSPs and FPGAs. A joint venture between Sundance DSP and the U.S. Navy SPAWAR Systems Center - Charleston has produced a system that enables adaptive multi-channel beamforming by utilizing closely coupled DSP/FPGA hardware. A model-based design method using the Simulink modeling tool, the PARS toolbox, and the Diamond environment and RTOS automate the translation from model to software/firmware.
Why Use Model-Based Design?
In a traditional communication design flow featuring embedded signal processing components, most errors are made in the research and development phases. However, most of these errors are only detected later, during the testing and integration of the system’s components. Model-based design seeks to eliminate this trend.
Under the principles of model-based design, stages may be divided as follows: 1) design, 2) modeling, simulation and prototyping, 3) code generation, 4) verification, and 5) implementation and system test.
These are performed hierarchically, and with the right tools, the outer stages can be performed in parallel. This process enables each component of the system to be modeled/generated/verified continuously throughout the development cycle. As changes in the design occur, the framework already exists to immediately observe the impact it has upon the entire system.
Beamforming Background and Design
The SPAWAR Systems Center - Charleston wished to have a rapid development system capable of exploring various types of beamforming methods on a large number of channels sharing the same spectrum. As a proof-of-concept demonstration, it was decided to have several Family Radio Service (FRS) FM radios transmit on the same channel at the same time and build a system capable of processing all of their signals. The FRS narrowband FM system operates in the 462.5625 to 467.7125 MHz band with 25 KHz channel separation.
At the top-level design of the system, a linearly arranged and equally spaced array of antennas forms the basic receiving structure (Figure 1). An array of programmable tuners shifts the spectrum of interest to a 21.4 MHz intermediate frequency (IF) for digitization. By using appropriate “look” directions, the beamformed system can selectively receive from any or all of the radios without any jamming occurring between them.
Due to the requirement for a large number of channels, the channelization architecture chosen for the FPGA is a polyphase filter bank. It implements a uniformly distributed multi-channel filter using an FFT. This implementation offers greater channel capacity compared to the traditional digital down-converter (DDC) for the same size silicon space. For optimum adjacent channel rejection, SPAWAR provided Sundance a custom filter design.
The DSP section implements a space-time adaptive beamforming algorithm. Beamforming allows arrays of sensors to discriminate between signals in one direction relative to background noise and interference in other directions. The important point to note is that the signals obtained from different antennas in the array differ in phase (determined by the distance between antenna elements) as well as in amplitude (determined by the weight associated with that antenna).
The beamforming architecture uses the Minimum Variance Distortionless Response (MVDR) beamformer (Figure 2). The adaptive algorithm enables the system to receive and separate multiple transmissions on the same frequency band based on direction of arrival of the signal of interest. The system adapts to changing conditions of the environment as well as the motion of interfering transmitters in space.
The Sundance modules used in this system include multi-channel analog-to digital converters, a dual-FPGA card, floating-point and fixed-point DSP solutions and a precision clock source (Table 1). All modules were attached to a carrier card. Several Sundance FPGA IP cores and application blocks and libraries were also used to reduce development time.
Having readily available acquisition hardware to collect real sampled data was a key factor in developing the polyphase filter coefficients.
MATLAB, from The MathWorks, was used to perform simulation and exploration of the mathematical operations of the entire process. This covered pre-filtering through the polyphase decomposition and FM demodulation. M-script is an interpretive language and results in quick visualization of any proposed implementation.
These simulations were used to define the specifications of the various processing “blocks,” as well as to clearly express to the team members what the underlying mathematics involved for each process was. Once these were defined, they could be modeled in Simulink, also from The MathWorks, quite straightforwardly.
The Simulink tool enables the hierarchical design and connection of processing blocks. These blocks represent the same expressions and operations of the mathematically oriented M-script, but with the emphasis on dataflow, inter-block connections and overall system architecture.
Parallel Application from Rapid Simulation (PARS) is a Sundance toolbox that allows MATLAB and Simulink users to rapidly design, simulate and generate code for a multi-DSP, multi-FPGA system. All development work is based on platform-independent models.
Diamond, from 3L, is an environment and RTOS based on communicating sequential processes. Initially targeting the transputer, it has evolved into the de facto standard OS of all Sundance DSP module implementations. Its ability to encapsulate the implementation of FPGA tasks within its process flow means that interfaces between FPGA and DSP are now completely ubiquitous and transparent. This enables closely coupled interaction between DSP and FPGA tasks.
Diamond tasks, which are derived from Simulink blocks, are mapped onto actual hardware by the Diamond configuration process (Figure 3). PARS assists in the translation by expressing the code generated by Simulink’s Real-Time Embedded Coder (for DSPs), HDL Coder (for FPGAs) or Xilinx System Generator (for FPGAs) as Diamond tasks.
“Hardware-in-the-loop” is a term used when selected parts of the model are exchanged with a data I/O system and an equivalent implementation on the target hardware. Modeling the processor and I/O constraints provides more accurate verification blocks.
In order to minimize development risk, subsystem groups of verified blocks can also be targeted for verification as part of a phased system integration plan. PARS takes advantage of the “divide-and-conquer” philosophy for large-scale development of multiple DSP/FPGA hybrid systems.
Finally, the entire system can be executed under controlled input vector conditions; result vectors are compared against the golden model executing in simulation. For every test vector input, the testbench can generate and compare a simulation/system output. Testbenches can be set to auto-generate test vectors to verify system behavior under expected as well as atypical conditions.
Once the hardware and software tasks are qualified under this process, it becomes a simple matter to render the entire system as an embedded application.
Diamond supports this step at the lowest level by providing the technology to encapsulate the software and firmware for all the DSPs and FPGAs in the entire system into a single executable image. Loading the entire processing network is simply a matter of providing this image to the “root” device of a multi-DSP, multi-FPGA network.
Simulink bridges the gap between the mathematics and the platform-independent model. PARS bridges the gap between the Simulink model and the deployable embedded system. Diamond makes it all possible.
As wireless revenues dominate the $8.3 billion 2006 DSP market, representing 72.5% of it, rapid development and deployment methods for communications systems continue to define reconfigurable hardware as the most relevant technology driving this market.
U.S. Navy, SPAWAR Systems Center - Charleston