VPX has become the de facto standard for the current generation of military embedded computing platforms. These systems include high-speed serial fabrics such as Serial RapidIO, PCI Express, or Ethernet. The initial VPX standards have focused on Gen1 Serial RapidIO, Gen 1 PCIe and XAUI with maximum baud rates of 2.5 to 3.125 Gbaud, Even supporting these rates is not a simple task often requiring a detailed signal integrity analysis and careful attention to the overall loss budget and the numerous signal impairments to ensure success the first time out. The new VITA 65 OpenVPX standard plans to add options for 5 and 6.25 Gbaud as well in order to support Gen2 Serial RapidIO and Gen 2 PCIe.

The recent adoption of IEEE 802.3ap 10GBase-KR, and the availability of silicon transceiver devices from a number of silicon vendors including AMCC, Broadcom and Xilinx, provide the basis for the next increment in VPX performance. This is the first standard communication protocol to support 10Gbaud per pair operation over a backplane, so it is a natural next step for VPX to implement 10GBase-KR for rugged applications. 10GBase-KR will require a signal integrity analysis paradigm shift from the classic time domain approaches (eye diagrams) to frequency domain and statistical approaches. Gen2 Serial RapidIO and Gen 2 PCIe include some of this thinking, but 10GBase-KR takes it to a whole new level.

Designing a compliant interoperable channel for 10.3 Gbaud over a single lane on a typical VPX backplane poses a number of technical challenges. To understand these challenges, it's helpful to looks at a representative VPX channel for 10GBase-KR compatibility using the IEEE 802.3ap compliance metrics. Understanding the tools and techniques for simulating a 10 Gbaud channel is also key.

VPX Channel Topology

VITA 46 systems come in a number of mechanical form factors. Regardless of the chassis arrangement, VPX backplanes are implemented in either 3U or 6U heights. The VPX REDI standards detail the slot pitch (0.8-in., 0.85-in., 1.0-in), the connector footprint and the pin assignments for differential pairs. A representative channel topology is shown in Figure 1. Backplane traces can range from 1 inch for adjacent slots to about 17 inches for a 21-slot, 0.8-inch pitch system. Typically, the maximum trace length is limited to control the maximum attenuation. For this study, we will consider a maximum backplane trace length of 17 inches.

VPX module trace lengths can range from roughly 1.5 inches with the transceiver placed just next to the connectors, to a practical maximum of about 4 inches. In terms of the frequency-dependent skin-effect losses, the module's trace length will often have more impact on the overall channel attenuation than the backplane traces because of the small etch geometries typically used on module PCBs. For this study, we assume that the module does not include a mezzanine connector/PCB in this path.

10GBase-KR-Compliant Channel

The IEEE 802.3ap specification defines a compliant channel with specific test point locations. The test channel does not include the transceiver package impairments or the discontinuities related to the BGA escape via or AC coupling capacitors. The test points that define a test channel are noted as TP1 to TP4 in the VPX backplane simulation topology diagram shown in Figure 2.

The 10GBase-KR specifies a number of frequency domain parameters in Annex 69B that can be used to evaluate channel conformance such as fitted attenuation, insertion loss deviation, return loss, and insertion loss to crosstalk ratio. The transmit and receive blocks have their own compliance metrics, which are not simulated or discussed in any detail here. The benefit of a compliant channel is that link performance can be evaluated with the assumption that the transceivers are known to be compliant. This study focuses exclusively on the VPX channel and will use behavioral transceivers integrated into the ADS channel simulation environment to replicate 10GBase-KR transmitter and receiver characteristics.

VPX Connector Modeling

VPX systems based on VITA 46 utilize a MultiGig-RT2 connector; this represents the vast majority of systems in use today. Recently, an alternative Viper connector has become available as well (VITA 60 draft), but it is not in widespread use today. Since the connectors share the same via footprints and pinouts, we will study both of these connectors.

The three-pair VPX connector model used primarily is this study was developed by the vendor using a full-wave EM modeler/solver. Pin assignments for VPX connectors are defined in the corresponding VITA 46 "dot" specification. The current VITA 46.x specification uses a common pin arrangement for differential pairs among all the fabric variants. A section of a differential VPX connector with the standard pin assignments is shown in Figure 3. The shaded portion of the connector diagram represents the section characterized in the connector S-parameter model. The fully coupled 3-pair via models were developed in a full-wave EM solver. Three via cases were developed to evaluate the impact of overall via length and stub length.

Simulation Methodology

The cascaded channel models are swept in the frequency domain in ADS and the behavior is plotted against the limits established in Annex 69B of the IEEE 802.3ap specification. The Annex 69B post-processing equations and limit expressions are implemented directly in ADS. The channel frequency domain model is also converted to time-domain to gain some insights as to the relative impedance discontinuity magnitudes.

Naturally, the largest impedance discontinuity feature of a conventional VPX channel is the connector and its footprint through vias. Dispersions within the connector create crosstalk and mode conversions. VPX backplane connectors have a 1.8 mm pitch which, along with a fairly large footprint via barrel diameter, will typically result in characteristic differential impedance as low as 85 ohms. The contact patch for the press-fit connector pin extends 20-30 mils into the top of the via creating an intrinsic top stub. The length tolerance of the connector pin contact zone effectively limits the depth of back drilling (or blind or stepped via length) and precludes top drilling.

The following VPX connector via cases shown in Table 1 were selected for evaluation because they allow routing on six of the eight available signal layers with a maximum of two levels of back-drilling. Note that in the low-volume, mission-critical VPX marketplace, the costs for back-drilling and low loss dielectric materials can generally be justified.

Channel Frequency Domain Behavior

The good SDD21 and SDD11 performance (Figure 4 and Figure 5) of the overall channel reflects the attention paid to limiting stub length as well as the use of a low loss dielectric material. Differential insertion loss at the Nyquist frequency of 5.156 GHz is in the range of -10.5 dB and -13 dB. The low overall channel attenuation allows designers to consider using less expensive dielectric materials. However, the additional signal-to-noise ratio afforded by the low loss material provides greater crosstalk margins as discussed in the following crosstalk section. This turns out to be an important consideration in meeting 10GBase-KR ICR (insertion loss to crosstalk ratio) limits. Also, the low overall differential insertion loss provides some flexibility for systems with longer trace lengths or more narrow trace widths.

Figure 4
Shown here is channel frequency domain SDD21 for three via cases.

Figure 5
Shown here is channel frequency domain SDD21 for three via cases.

Given the low passband ripple and the relatively low attenuation in the signaling band with the worst-case LVLS configuration, the following frequency domain analyses focus on this via scenario with the exception of the crosstalk evaluation where the via length has a considerable impact on ICR margins. The channel also has good margin to the IEEE 802.3ap recommended return loss limits.

Frequency Domain Crosstalk Characteristics

Note that in the VPX differential pair pinout, the C:D pair has two adjacent near end aggressors (E:F pairs) and two adjacent far end aggressors (A:B pairs), so it is a reasonable worst-case pair for crosstalk evaluation. The frequency domain differential NEXT and FEXT crosstalk performance was evaluated using two symmetrical, uncorrelated aggressor pairs acting on the C2:D2 pin pair. The power sums of the individual aggressors were calculated as specified in IEEE 802.3ap, Annex 69B. The PSFEXT and PSNEXT contributions were then power summed to form the overall crosstalk (PSXT).

The architects of the IEEE 802.3ap specification did not define strict crosstalk limits. Instead, acknowledging that some less lossy channels could tolerate higher crosstalk levels, they defined a limit based on the ratio of insertion loss to the total crosstalk (ICR). This measure is analogous to Signal-to-Noise Ratio (SNR). Given the pitch and via barrel diameter of VPX connectors, this measurement method can be of particular benefit in VPX systems. As mentioned above, shorter vias tend to have substantially lower crosstalk. A system designer can trade off the costs of more expensive dielectric materials against a more restrictive routing policy where the 10.3 Gbaud traces are routed exclusively on the top most layers. In the test case, IEEE 802.3ap ICR limits are met with a low loss (dissipation factor of .0075 and 2.5 GHz) dielectric material without introducing the layer routing restrictions mentioned above.

10GBase-KR Equalization

IEEE 802.3ap specifies that transceivers implement, at minimum, 3-tap Feed Forward Equalization (FFE) in the transmitter and acknowledges the probable need for a multi-tap Decision Feedback Equalizer (DFE). Most 10GBase-KR transceivers will implement both FFE and DFE and will likely have a linear equalization stage in the receiver as well.

With three different equalization methods available in most 10GBase-KR transceivers, how is one chosen over another? The worst-case channel described here could be generally characterized as having low attenuation, with low passband ripple, but with only marginal crosstalk immunity. Continuous Time Linear Equalization (CTLE) is not the best choice since the channel is not highly attenuated and linear equalization amplifies noise and crosstalk along with the signal. FFE is an appropriate choice since it provides both pre- and post-cursor equalization.

The number of taps implemented by silicon vendors will vary, but it is probably safe to assume that most will provide at least two pre-cursor and two post-cursor taps. Assuming a limited number of taps, FFE will probably not be able to "reach" the ripple out at the 4.5ns point in the SBR plot. DFE can provide the additional post-cursor equalization. The main draw back with DFE is that it, by nature, will tend to propagate bit errors, especially when the coefficients become large  10G-Base-KR defines an optional Forward Error Correction (FEC) encoding sublayer for counteracting multi-bit burst errors. In addition, FEC can improve the effective BER performance of marginal channels.

Equalization Performance

First, eight statistical simulations were performed on just the through channel pair (the crosstalk pairs were just terminated on both ends). The eye density and contour at BER 10-12 (inner-most opening outline) plots for simulation case 7b is shown in Figure 6. The DFE transition responses are evident at zero-crossings. As mentioned earlier, faster rise/fall times will increase the SNR and horizontal opening (at the expense of crosstalk margins and power plane noise coupling). 10GBase-KR specifies a transition time of 24 to 47 pS. At 40 pS, the simulations were performed closer to the worst-case end of the allowable range.

Although VPX is typically operated at 2.5 to 3.125 Gbaud today, the simulations performed indicate that VPX can support the IEEE 802.3ap 10GBase-KR 10.3 Gbaud signaling speed. Advanced, adaptive equalization is the key to obtaining strong, reliable performance despite some inherent limitations of the VPX platform. Mapping 10GBase-KR to VPX requires very careful attention to high-speed design details. The VPX topology simulated in this study is, not surprisingly, sensitive to crosstalk impairments, but with careful attention to via tuning, it is fortunately free of large insertion loss ripple associated with connector-related impedance discontinuities. On more complex topologies, such as modules with transceivers located on a mezzanine card, designers will be faced with some difficult decisions regarding material selection, routing restrictions, spacing rules, trace geometries, and perhaps even connector pin assignments. Designers must pay particular attention to via impairments, both in terms of their overall length and their stub length.

System implementers must come to understand how to best apply equalization on a link-by-link basis. Fortunately, adaptive FFE and DFE equalization methods implemented in current 10GBase-KR transceivers will make this potentially complex task routine. We predict that 10.3 Gbaud interfaces will become as common on VITA 46 platforms as 3.125 Gbaud links are today. The VITA 68 group chaired by Bob Sullivan from Hybricon is currently working to define a VPX compliance channel to allow higher rates on VPX, initially aimed at Gen 2 SRIO and PCIe at 5-6.25 Gbaud, but with an eye toward 10GBASE-KR as well.

Hybricon
Ayer, MA.
(978) 772-5422.
[www.hybricon.com].