Gone are the days when processor architectures sporting multiple CPU cores on the same device were exotic and unique. They’ve now moved solidly into the mainstream desktop and sever realms. And many military applications have an immediate need for the level of computing muscle such devices provide. That trend has all but eliminated the gap between the emergence of a microprocessor product line and the demand for it among the military embedded computing realm. With the dual-core, multicore CPU trend firmly established in the general computing market, embedded board vendors have followed up quickly with boards based on those CPUs like the Core2Duo, i7, QorIQ and others. The product roundup here shows a representative sample of multicore boards on a variety of embedded form factors—including cPCI, AMC, VPX, VME and ATCA.
There’s no doubt that the multicore transition in the microprocessor world is all but complete. The road maps of the leading processors show that all roads lead to architectures sporting multiple CPU cores on the same device. Because the trend is fundamental across all processor vendors, issues surrounding multicore processing must be faced by all high-end computing applications today or in the near future. Many military applications have an immediate need for the level of computing muscle such devices provide.
For many years microprocessor designers made clever use of the ever-increasing number of transistors that bless semiconductor fab advances. They successfully wrung the greatest possible performance increases out of their designs by refining their superscalar architectures and lengthening pipelines. Those techniques brought processors from 100 MHz of a decade ago all the way to the 1 GHz and more that we’re at today. Today, for reasons like power density and other physical issues—all those techniques aimed at making single microprocessors faster no longer have the return that they once had. That led processor architects to realize that the most efficient way to leverage the Moore’s Law “guarantee” of increasing transistor counts is to pack multiple processing units on the same die.
Applications that have been first to reap the rewards of multicore technology are compute-intensive applications such as sonar, radar, SIGINT and UAV control systems, along with several others. The Aegis Modernization (AMOD) program is another example. AMOD is an upgrade to the Aegis Weapon System (AWS), the automated segment of the Aegis Combat System (ACS). Using 2.16 GHz Core2Duo-based conduction-cooled CompactPCI boards for its processing needs, the AMOD upgrade is intended for DDG-51 Arleigh Burke-class Aegis guided missile destroyers such as the USS Stethem (DDG 63) (Figure 1).
Figure 1
Aegis Modernization (AMOD) program is making use of Core2Duo-based conduction-cooled CompactPCI boards for processing needs aboard DDG-51 Arleigh Burke-class Aegis destroyers such at the USS Stethem.
While the trend toward multicore processing is nearly universal, there are two fundamentally different approaches to the trend. The more mainstream processor vendors like Intel, Freescale and AMD are moving to an SMP (symmetric multiprocessing) approach where each core runs a separate program thread. In an application that happens to have two completely unrelated threads, one of them can be waiting for I/O while another can be calculating. The other multicore approach, what academics call “tiled” processors, hasn’t been as popular as SMP because of the complexity of programming such systems.
Discuss
Jeff, I really enjoyed reading your editorial, and how multicore systems have been deployed as part of the Aegis Modernisation Programme. I've linked to your article from my latest blog post: http://blogs.windriver.com/parkinson/2010/05/multicore-called-up-for-active-service.html Best Regards, Paul
Mats May 19, 2010 – 12:33pm
There is really only one tiled processor on the market and it's the Tilera TILE64(Pro). The programming model of this architecture is very much SMP and most code developed for Intel and other SMP multicore processors could just be recompiled and run without modifications, although given the scale of parallelism (64 cores instead of a handful) most often require careful tuning.

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Paul Parkinson May 19, 2010 – 8:51am