Waveform-intensive applications like sonar, radar, SIGINT and SDR demand ever more signal processing power. Faster DSPs coupled with a broader range of IP cores and development tools for FPGAs are appearing in board-level subsystems with new DSP system architectures.
New FPGAs are helping military radar system engineers boost performance in two major ways. These vital building blocks speed signal processing algorithms and help connect radar systems to high-speed switched serial fabrics.
The DoD’s JTRS initiative gave birth to SDRs, originally built with DSPs and general-purpose processors. New DSP process technology breakthroughs, combined with FPGAs, are fueling
reductions in SDR cost, size, complexity and power consumption. Taking advantage of these, engineers are building a new generation of JTRS radios for environments with dense foliage or urban settings.
The demands of blending multi-channel and high throughput requirements place heavy demands on military sonar designs. 3U cPCI and FPGAs smooth the upgrade tasks.
Today’s demanding vibration and shock requirements call for complex active control systems. Modeling schemes help streamline test and simulation efforts.
A lack of standards for the correct implementation of the stress test techniques known as HALT and HASS has resulted in widespread confusion. When implemented correctly, HALT and HASS provide a fast, cost-effective path to greater product reliability and customer satisfaction, as well as reduced warranty costs.
More expensive, complex functions like digital transmitters, digital receivers and wideband ADCs are being implemented as PMC modules, while FPGAs are being used to expand their functionality and versatility.
