Enabled by a strong partnership with innovative Andes Technology Corporation
IAR Systems announces initial support for the draft RISC-V P extension in its powerful development tools IAR Embedded Workbench® for RISC-V. Thanks to this early support for the extension as implemented by Andes Technology, a Premier Founding member of RISC-V International, developers can take advantage of a leading development toolchain when starting to develop applications based on the new RISC-V core extension.
The RISC-V International is in the process to standardize a series of standard extensions beyond the integer base instructions which can be implemented or omitted as desired depending on the design goals (for example energy/area/performance/storage goals). The RISC-V P extension is designed to be a standard extension for Packed-SIMD instructions. The extension targets efficient media processing for audio, voice, and images, and is a generalization of a Packed-SIMD extension donated to the RISC-V International by Andes Technology Corporation.
“We have achieved around 9x performance boost of CIFAR-10 inference with RISC-V P extensions. Packed-SIMD provides edge processors more computing power with higher energy efficiency and minimal increase in cost, and such capability empowers edge devices to deal with voice and slow video processing,” comments Dr. Chuanhua Chang, the Chair of RISC-V P extension Task Group and Head of Architecture Division of Andes Technology Corporation. “We are excited to partner with IAR Systems to further accelerate the performance of applications based on RISC-V in general and P extension in particular. Together, we provide powerful solutions that will enable our customers to meet and exceed their project requirements.”
“Andes is a strong and active player in the RISC-V community, and together we have a lot to offer with regards to performance,” says Anders Holmberg, General Manager Embedded Development Tools, IAR Systems. “By jointly supporting the P extension, we bring extended possibilities for powerful RISC-V development and add new ways to optimize application and hardware performance.”
RISC-V is a free and open instruction set architecture (ISA) based on established Reduced Instruction Set Computing (RISC) principles. Launched in 2019, IAR Embedded Workbench for RISC-V provides excellent optimization technology, helping developers ensure the application fits the required needs and optimize the utilization of on-board memory. This also enables companies to aggregate value by adding functionality to an existing platform. To ensure code quality, the toolchain includes C-STAT® for integrated static code analysis. C-STAT can help prove compliance with specific standards like MISRA C:2004, MISRA C++:2008, and MISRA C:2012, as well as to detect defects, bugs, and security vulnerabilities as defined by the Common Weakness Enumeration (CWE) and a subset of CERT C/C++.
The current version of IAR Embedded Workbench for RISC-V provides support for RV32 and RV32E 32-bit RISC-V cores and extensions. Future releases will include 64-bit support, as well as functional safety certification and security solutions.