Announcing Graph Memory Engine™ Running on Xilinx UltraScale+ with TCAM Compiler
The Packet Classification Platform will make use of MoSys’ innovative virtual accelerator, the Graph Memory Engine (GME), for performing embedded search and classification of packet headers as an alternative to TCAM functions. The platform includes the GME and software that compiles TCAM images into graphs for GME processing using a common API for portability. The GME is provided as a family of implementations ranging from a pure software version for maximum flexibility and capacity, RTL for use in a Xilinx FPGA for hardware performance, and a maximum performance RTL solution connected to a MoSys Programmable HyperSpeed Engine (PHE) with its 32 embedded RISC cores. The initial FPGA versions of the GME are compatible with Xilinx UltraScale+ and utilize a common RTL interface to facilitate platform portability.
The search performance on an UltraScale+ FPGA with MoSys PHE can result in up to 100x performance over software solutions running on host CPUs with DRAM, which are bottlenecked by random accesses of memory. The PHE version provides enough performance to support two 100G ethernet ports.
“Along with making acceleration available to a wider set of environments, MoSys enables the software designer to make use of hardware performance without developing firmware or RTL,” noted Michael Miller, MoSys’ chief technical officer. “Moreover, similar to the GME, the same approach can be applied to a wide variety of advanced embedded applications including key value pair databases, networking search functions, machine learning, computation and algorithm acceleration, all of which can run on different hardware platforms.”
New platforms will be rolled out over the next few quarters to address other markets. Target applications include acceleration cards, 5G edge compute, aerospace and defense, advanced video, high-performance computing and other data-driven applications.
“We are delighted to see MoSys expanding its product strategy in this direction,” noted Farhad Shafai, vice president, communications markets, Xilinx. “Our industry-leading FPGAs already have proven experience interfacing with MoSys’ Bandwidth Engine serial-memory devices to accelerate networking and security applications. We look forward to collaborating with MoSys on its new platform to enable customers even higher, more scalable performance and flexibility using our advanced adaptable solutions.”
MoSys is currently in discussions with early access customers and expects to formally release the products in the first quarter of 2020.
At the recent series of Xilinx Developer Forums, MoSys successfully demonstrated its packet classification and layer 2 forwarding capability targeted at FPGA-based SmartNIC, router, switching, security and cloud applications. The interactive demonstration featured a TCAM compiler, classifier and a Layer 2 forwarding database running on a MoSys PHE connected to a Xilinx VU9P UltraScale+ FPGA on a PCIe card plugged into a standard server box.