QuickLogic Corporation has released a new Aurora eFPGA development tool suite version. The Aurora 2.1 Development Tool Suite is based on a fully open-source implementation for scalability, longevity, and complete code transparency. It supports all significant HDLs, including Verilog, System Verilog, and VHDL.
About the Aurora 2.1 Development Tool Suite
The new version is based on open-source synthesis (Yosys), Versatile Place and Route (VPR), and bitstream generation (OpenFPGA) software. The fully integrated suite of tools enables FPGA designers to go from RTL-to-bitstream for QuickLogic’s eFPGA IP. The Aurora eFPGA user tools also support an architecture analysis mode, allowing the users to tune the architecture for their application instead of being forced into a ridged fixed-size tile approach.
– Enables Architectural Trade-Offs – Ensures that the generated eFPGA IP has optimal
logic (LUTs), BRAM, and DSP blocks to meet each customer’s unique eFPGA
- More Transparency – Because Aurora is based on open source, the code is highly inspectable, enabling continuous improvement by the development community.
- Flexibility – Publicly auditable code leads to higher quality software and allows for the merit-based addition of features by the community and the option to make enhancements that suit each customer’s needs.
- Future-Proof – Aurora uses readily available open-source components that the broader community is actively improving upon. Access to source code gives the ultimate user control of the future.
“QuickLogic remains committed to open source, and our new Aurora 2.1 Development Tool Suite underscores that mission,” said Mao Wang, senior director of product development at QuickLogic Corporation. “Now, SoC developers can combine the advantages of open-source tools with the dramatic flexibility benefits of embedding FPGA technology into their devices to improve device lifecycles and enhance profitability.”