DDC-I announced that it will port its Deos DO-178C safety-critical real-time operating system to Texas Instruments’ Jacinto™ 7 family of processors. Jacinto 7 processors running Deos™ provide an ideal platform for developing, deploying, and certifying DO-178C avionics software with the most demanding I/O, networking, and control requirements.
The Jacinto 7 processor family features a heterogeneous architecture optimized for control node and intelligent sensor applications. Featuring Arm® Cortex®-A72 cores and a mix of fixed and floating-point DSP cores, Jacinto 7 processors are also equipped with matrix multiplication accelerators for machine learning, integrated ISP, and vision processing. While primarily intended for automotive and industrial applications, the Jacinto 7 processor family’s integrated feature set also makes it an excellent choice for avionics systems.
“Jacinto 7 processors provide a unique blend of high-performance multicore computing, co-processing, and versatile I/O that make it superb for avionics applications requiring data fusion, array processing, and other advanced control and sensor functionality,” said Greg Rose, vice president of marketing and product management at DDC-I. “Deos cache partitioning, time/space partitioning, and system redundancy features allow avionics developers to take full advantage of the Jacinto 7 processors’ multicore computing, I/O, coprocessing, and security features while reducing worst-case execution time to achieve the highest level of safety-critical operation.”
Deos is a safety-critical embedded RTOS that uses patented technology to deliver the highest possible CPU utilization on multi-core processors, including a broad range of Arm®-based processors and cores. First certified to DO-178 DAL A in 1998, Deos features hard real-time response, time and space partitioning, ARINC-653, and POSIX interfaces, all in a FACE™ Conformant Safety Extended and Safety Base Profiles. With an emphasis on multicore applications, Deos scales well in the gamut of avionics applications, from highly deterministic deeply embedded FADECs (Full Authority Digital Engine Control) and flight controls to complex high throughput displays and mission computers.
DDC-I’s SafeMC™ technology extends Deos’ advanced capabilities to multiple cores, enabling developers of safety-critical systems to achieve best-in-class multi-core performance without compromising safety-critical task response and guaranteed execution time. SafeMC employs a bound multiprocessing (BMP) architecture, safe scheduling, and cache partitioning to minimize cross-core contention and interference patterns that affect the performance, safety criticality, and certifiability of multi-core systems. Together with Deos’ unique redundancy features, avionics systems developers can develop highly robust systems using Multi-Core Processors (MCP), as specified by the Certification Authorities Software Team (CAST).